Esai-esai Nano

September 6, 2005

90 nm and beyond

Filed under: IC design — estananto @ 11:25 pm

This time I want to discuss something technological.
If you are aware enough at recent computers’ processor development, you’ll see that now the manufacturers sell also the dimension of their transistors in their chips. Intel or AMD, for example, boast their ability to build chip consists of 90-nm transistors or at least 130-nm transistors. What does it mean?
The smaller transistor makes you to put more transistors in the same area. More transistors can be designed into more functionalities. More functionalites enhance complexity. You can have more applications with more features. In one version of Intel Pentium 4, there are at least 55 millions transistors inside. Just imagine!
Smaller transistors need also lower (operational) power per transistor for the same performance. But the problem is, as mentioned above more and more transistors are packed in the same – or smaller – area. These will produce more heat, and according to one estimation, if nothing is done then heat per area in a processor would be as high as that of rocket’s nozzle. The other effect is: when you have smaller channel of CMOS transistors, you have also more leakage current – and that means also leakage power in stand-by. If the transistor is not active, you will have leakage and this would be serious challenge to future development of processor. Theere are some ways to control leakage power: to use some high-threshold transistors in non-critical path, to use bias voltage in the “body”, using “sleep-mode” when the circuit in stand-by, or putting insulator between substrate and transistors called Silicon on insulator (SOI). There are, of course – still many ways to explore to overcome this problem.

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1 Komentar »

  1. Mas Nano,
    Terimakasih atas kunjungan dan komentar di blog saya. Komentar yang menggugah semangat.
    Sekali lagi, makasih.

    Komentar oleh Rizqon Khamami — September 7, 2005 @ 12:11 pm | Balas


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